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Si5 52
3. Ordering Information
The Si552 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
V DD . Specific device configurations are programmed into the Si552 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si552 VCXO series is supplied in an industry-standard, RoHS-compliant,
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
552
X
X
XXXXXX
D
G
R
R = Tape & Reel
552 Dual VCXO
Product Family
1 st Option Code
Blank = Trays
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Letter
6-digit Frequency Designator Code
Two unique frequencies can be specified within the following bands of frequencies: 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to dual XOs programmed
with the lower frequency value selected when FS = 0, and the higher value when FS = 1.
Six digit codes < 000100 refer to dual XOs programmed with the higher frequency value
3.3
Code
A
B
C
VDD
3.3
3.3
DD
Output Format
LVPECL
LVDS
CMOS
selected when FS = 0, and the lower value when FS = 1.
2 nd Option Code
D
E
3.3
2.5
CML
LVPECL
Temperature
Stability
Tuning Slope
Kv
Minimum APR
(±ppm) for VDD @
F
2.5
LVDS
Code
± ppm (max)
ppm/V (typ)
3.3 V
2.5 V
1.8 V
G
H
J
K
2.5
2.5
1.8
1.8
CMOS
CML
CMOS
CML
A 100 180 100
B 100 90 30
C 50 180 150
D 50 90 80
75 25
Note 6 Note 6
125 75
30 25
E 20 45 25
Note 6 Note 6
Notes :
CMOS available to 160 MHz.
F 50 135 100
G 20 356 375
H 20 180 185
J 20 135 130
K 100 356 295
M 20 33 12
75 50
300 235
145 105
104 70
220 155
Note 6 Note 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x V DD x tuning slope.
4. Nominal Absolute Pull Range ( ± APR) = Pull range – stability – lifetime aging
= 0.5 x V DD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
Example Part Number: 552AF000108DGR is a 5x7mm Dual VCXO in a 6 pad package. Since the six digit code (000108) is >
000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3V supply and LVPECL output.
Temperature stability is specified as ± 50 ppm and the tuning slope is 135 ppm/V. The part is specified for a -40 to +85 C° ambient
temperature range operation and is shipped in tape and reel format.
Figure 1. Part Number Convention
10
Rev. 1.1
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相关代理商/技术参数
552AD000112DG 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/644.53125MHZ VCXO LVPECL 6PIN - Trays
552AD000112DGR 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/644.53125MHZ VCXO LVPECL 6PIN - Tape and Reel
552AD000116DG 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/669.32658MHZ VCXO LVPECL 6PIN - Trays
552AD000116DGR 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/669.32658MHZ VCXO LVPECL 6PIN - Tape and Reel
552AD000123DG 制造商:Silicon Laboratories Inc 功能描述:
552AD000123DGR 制造商:Silicon Laboratories Inc 功能描述:
552AD000126DG 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays
552AD000126DGR 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel